(a) Field of the Invention
The present invention relates to a semiconductor device having a HMP (high-melting-point) metal gate suited to a dual-gate structure wherein a P-channel transistor and an N-channel transistor share a gate structure. The present invention also relates to a method for manufacturing such a semiconductor device.
(b) Description of the Related Art
An LSI having a gate electrode including a HMP metal, such as tungsten (W), is known to have a higher operational speed and a higher resistance against the heat applied in the fabrication steps thereof. The HMP metal gate is generally formed by consecutively depositing a thin polysilicon film and a HMP metal film having a lower electric resistance on a gate oxide film.
It is known in such an LSI that a HMP metal silicide is formed by depositing a HMP metal film directly on a polysilicon film and performing a high-temperature heat treatment thereto, which causes the HMP metal to react with silicon at the interface between the films. The HMP metal silicide film has a relatively higher electric resistance however, and accordingly, the formation of the HMP metal silicide film should be suppressed for achieving a higher operational speed of the transistors in the LSI. Patent Publication JP-A-11(1999)-233451 describes a technique for suppressing the silicide reaction of the HMP metal during the heat treatment, by forming a HMP metal nitride film, such as including WN, at the interface between the HMP metal film and the polysilicon film.
However, during the heat treatment after formation of the metal nitride film directly on the polysilicon film, the HMP metal nitride film strongly reacts with Si in the polysilicon film, thereby forming a thick HMP metal silicide nitride film. Although the thick HMP metal silicide nitride film has an excellent barrier function, the thick HMP metal silicide nitride film may have a higher electric resistance due to a possible high resistivity of the HMP metal silicide nitride depending on the composition thereof or the layered structure of the gate electrode. The higher electric resistance prevents the semiconductor device from achieving a higher operational speed.
The present inventor proposed a technique for forming a gate electrode in Patent Publication JP-A-2003-163348. In the publication, a HMP metal silicide film having a relatively lower electric resistance is interposed between the polysilicon film and the HMP metal nitride film, followed by performing a heat treatment for the layered structure as a whole including the HMP metal silicide film, HMP metal nitride film and HMP metal film to form a thin HMP metal silicide nitride film.
The present inventor further studied the technique for forming the gate electrode in the LSI and found that the technique described in JP-A-2003-163348, if applied to a LSI having a dual-gate structure and thus including an N-channel area and a P-channel area located adjacent to one another, causes the problem of increase in the interface resistance and increase in the film thickness in terms of the thickness of the silicon.
The above problem results from the fact that the diffusion coefficient of the impurities is higher in the HMP metal silicide film than in the silicon film by three to six orders, and that the N-type impurities in the polysilicon film in the N-channel area and the P-type impurities in the polysilicon film in the P-channel area are absorbed by the HMP metal silicide film during the heat treatment, causing a bilateral diffusion of the N-type and P-type impurities between the N-channel area and the P-channel area. It is also found that the amount of the impurities diffused from the P-channel area to the N-channel area of the gate electrode in the pair is especially large, to thereby reduce the electric conductivity of the gate electrode.